Data handling system



y 1967. D. E. HASELWOOD ET AL 3,323,112

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dtfamey United States Patent 3,323,112 DATA HANDLING SYSTEM Donald E. Haselwood, Deerfield, and Carl M. Solar, Chicago, IlL, assignors to A. C. Nielsen Company, Chicago, Ill., a corporation of Delaware Filed Nov. 12, 1964, Ser. No. 410,475 13 Claims. (Cl. 340-1725) This invention relates to a data handling system, and, more particularly, to a data handling system including new and improved means for transmitting and receiving data.

The copending application of Charles H. Currey, Ser. No. 232,684, filed Oct. 24, 1962, now Patent No. 3,289,- 170 which application is assigned to the same assignee as the present application, discloses a system for collecting data relating to the on-oir and tuning conditions of wave signal receivers geographically remote from a central station and for automatically transmitting the data to the central station in response to the receipt of an individually addressed interrogation from the central ofiice. The system shown in this application uses a pulse width data transmitting and receiving technique in which the timing of the transmitting and receiving operations requires a relatively large number of timing circuits, such as monostable circuits, that must be capable of maintaining rather precise tolerances under varying operating conditions in the field. Although this can be done, it increases the size and cost of the home transponder or transmitreceive unit.

Accordingly, one object of the present invention is to provide a new and improved data handling system.

Another object is to provide a data handling system including new and improved data transmitting and receiving means.

A [further object is to provide a data handling system including a home transponder unit capable of being time synchronized from a conventional alternating current potential source.

Another object is to provide a data receiver for use with variable duration signals including new and improved means for checking and timing the received signals.

Another object is to provide a data handling system in which a shift register is sequentially loaded with address signal bits under the control of signaling line transitions, and the bits stored in the shift register are checked in parallel to determine the presence or absence of a correct address.

Another object is to provide a data handling system including a shift register which stores address signal bits during an address receiving operation and operates as an output steering device during a data transmitting operation.

Another object is to provide a data handling system of the type having a transmitting relay operated to open and close a signaling channel during transmitting operations and timing means responsive to an inadvertent interruption of the signaling channel for controlling the relay to reestablish channel continuity.

In accordance with these and many other objects, an embodiment of the invention comprises a data handling system including a central olfice and a plurality of remote stations or home transponder units connected to a commonsignaling channel or loop. The home transponder units are associated with wave signal receivers and collect information such as that relating to the tuning condition or the on-off condition of the connected receiver or receivers. This information is periodically transmitted in sequence from the home units to the central ofiice in which it is compiled and made available (for use. The home units are rendered efiective in sequence to transmit the collected data to the central office by the sequential transmission from the central office of an address individual to each of the home units.

The data handling system embodying the present invention uses variable Width or duration pulse signals to represent binary 1s and Os. For an example, the presence or absence of a signal for a long duration can represent a binary 1 while the presence or absence of a signal for a short interval can represent a binary 0. When the data collected in the remote unit is to be transmitted to the central station, the central station transmits a combination or permutation of long and short signals in accordance with the address of a desired remote unit. These signals are received at all of the homes on the signaling channel or loop, and the duration of these signal is checked by timing means driven from a conventional 60 cycle alternating current potential. Each binary 1 or 0 bit established by the timing means is supplied to an input stage of a shift register, and each hit is then shifted to subsequent stages of the register in response to line transitions representing the end of one pulse width or time interval and the beginning of the next. In this manner, the shift register is loaded with a permutation or combination of binary 1s and 0s in accordance with the transmitted address. Following the completion of the transmission of the address, the identical addresses stored in the shift registers in all of the home units are compared with the different known addresses of these units to determine the presence of a coincidence establishing the one of the home units called from the central ofiice.

In the single home unit in which the transmitted address corresponds to the known designation individual to this home unit, the shift register is cleared and a single bit is advanced through the shift register from its first to last stages. The stages of the shift register now function as a commutator or steering device to sequentially enable a plurality of gates coupled to a data storage means in the home. During thi commutating operation, the transmitting relay in the connected home unit is operated to supply long and short duration signals to the signalling channel in accordance with a binary coded representation of the on-off and tuning condition information stored in the home unit. When the shift register has completed such a cycle of operation, the home unit is restored to a normal condition.

Many other objects and advantages of the present invention will become apparent from considering the following detailed description in conjunction with the drawings in which:

FIGS. 1 and 2, when placed side by side, form a complete logic diagram of the data handling system embodying the present invention;

FIGS. 3A and 3B illustrate a logical symbol and typical circuit for a control flip-flop used in the logic diagram shown in FIGS. 1 and 2;

FIGS. 4A and 4B are a logic symbol and typical circuit diagram of a bistable circuit used in a shift register forming a part of the system shown in FIGS. 1 and 2; and

FIG. 5 is a diagram illustrating the manner in which FIGS. 1 and 2 are placed adjacent each other to form a complete logic diagram.

The details of the data handling system embodying the present invention are illustrated in FIGS. 1 and 2 by the use of logic diagrams in which the various circuit components are shown in logic schematic form. In the logic diagrams, these circuit components, such as a flip-flop, are represented by a particular logic symbol. Logic symbols together with typical circuit arrangements represented by the logic symbols for certain of the components shown in FIGS. 1 and 2 are illustrated in FIGS. 3A, 3B and 4A, 4B of the drawings. Each of these figures includes both an illustration of the logic symbol and a typical circuit represented by the symbol. Although the illustrated representative circuits are conventional in design and well known in the art, a brief description of certain of the circuits is set forth below.

The logic symbol for a control and counter flip-flop is illustrated in FIG. 3A, and a typical circuit for this flip-flop is illustrated in FIG. 3B. The control flip-flop includes a bistable circuit including a pair of transistors and 22 that are alternately placed in conduction. The emitters of the transistors 20 and 22 are connected to a source of reference potential, such as ground, and the collectors thereof are cross-coupled with the base electrodes. Assuming that the transistor 20 is normallyin a conductive condition so that substantially ground potential is applied to an output terminal E, a positive-going signal applied to a terminal A or a positive signal applied to a terminal C biases the base of the transistor 20 positive with respect to its emitter to place this transistor in a nonconductive condition. At this time, the potential applied to the base of the transistor 22 becomes more negative to place this transistor in a conductive condition. At this time, a more negative potential is applied to the output terminal E, and substantially ground potential is applied to an output terminal D. The subsequent application of a positivegoing pulse to either the complementing input terminal C or a positive signal to another input terminal B places the transistor 22 in a nonconductive condition so that the transistor 26 is returned to a conductive condition. In this state, the bistable circuit or flip-flop applies a more negative potential to the output terminal D and ground potential to the output terminal E. The flip-flop circuit is energized by a nominal twelve volt positive and negative potential supply.

In the logic symbol shown in FIG. 3A, the shaded portion of the rectangle illustrates the application of a more positive or ground potential to the output terminal D and the application of a more negative potential to the output terminal E in the condition of the circuit in which the transistor 22 is in a conductive state. The arrangement of the input and output leads in the logic symbol shown in FIG. 3A is such that the application of positive or positive-going signals to either of the input terminals A or B places theconnected portion of the rectangle at ground potential. In other words, the application of a positive signal to the terminal B places the output terminal E substantially at ground potential. The application of a positive-going pulse to the input terminal C switches the conductive state of the transistors 20 and 22 and reverses the polarities of the potentials applied to the output terminals D and E.

T he logic symbol for a shift register flip-flop or bistable circuit is shown inFIG. 4A of the drawings, and a typical circuit for this flip-flop is illustrate-d in FIG. 4B. The bistable circuit shown in FIG. 4B is substantially identical to the circuit shown in FIG. 3B and includes a pair of transistors 30 and 32 having grounded emitters and crosscoupled base and collector electrodes. The flip-flop includes a pairof enabling input leads A and B, which are alternately or selectively supplied with a potential near ground or a negative potential, and a pulse input terminal C. An output terminal E returns substantially to ground potential When the transistor 32 is placed in conduction and drops to a more negative potential when the transistor 32 is placed in a nonconductive condition. An output terminal F is provided with opposite polarity signals relative to the terminal E under the control of the transistor 3t). A reset terminal D is provided with a positive pulse to place the transistor 32 in a nonconductive state and the transistor 30 in a conductive condition in the normal or reset state of the circuit.

Assuming that the input terminals A and B are coupled to the output terminals E and F of the flip-flop in a preceding state so that ground potential is applied -to the terminal A and a negative potential is applied to the terminal B, a diode 34 is biased in a reverse direction, and a diode 36 is enabled. Thus, when a positive-going pulse is applied to the count or shift input terminal C, it is forwarded through the diode 36 to place the transistor 30 in a nonconductive state and the transistor 32 in a conductive state. The application of additional input pulses to the input terminal C does not change the state of the flip-flop until the enabling potentials applied to the terminals A and B are reversed. When these potentials are reversed, the next pulse applied to the terminal C places the transistor 32 in a nonconductive condition and places the transistor 30 in a conductive condition.

In the logic block shown in FIG. 4A, the input terminal D is shown connected to the shaded portion of the rectangle to which the output terminal F is connected to represent the fact that this terminal is normally placed at ground potential when a positive pulse is applied to the terminal D. The input terminal C is coupled to both halves of the rectangle forming the logic symbol. The output terminal E is connected to the open portion of the rectangle to represent the fact that this terminal is at a more negative potential in the normal condition of the flip-flop.

Referring now more specifically to FIGS. 1 and 2 of the drawings, therein is illustrated a data handling system including a central office 40 terminating a signaling line or channel 42 to which a plurality of geographically remote home units or transponders, such as a home unit 44 and a home unit 46 whose details are illustrated in FIGS. 1 and 2, are connected. Each of the home units 44 and 46 includes conventional means for supplying an encoding network 48 with signals representing the on-off condition and the tuning condition of one or more connected wave signal receivers, such as a television or radio receiver. The encoding network 48 shown in FIG. 2 is supplied with signals representing the on-off condition of two television receivers as well as a binary coded representation of the channel or station to which each of the receivers is tuned. This information is supplied by the designated blocks shown to the right of the encoding network 48 in FIG. 2.

When this information is to be transmitted from the remote units 44 and 46 to the central office -ltl, this oilice transmits an address over the signaling line 4-2 in the form of long and short duration signals representing binary 1s and binary 0s in accordance with the individual address of the desired home unit, such as the unit 46. The durations of these signals are marked off or delineated by transitions between mar and space or space and mar conditions on the signaling line 42 and are applied in common to all of the home units 44 and 46. In response to the transition on the line 42 marking the beginning of the initial long space signal forming a start control signal, a timing circuit indicated generally as 49, which is driven by a conventiional 6O cycle alternating current potential supply, is reset to a normal condition to initiate a timing cycle in the home unit 46. This home unit is also prepared for the reception of an address. The timing circuit 49 is operative during the long space signal to reset 9. shift register indicated generally a 50 to a normal condition, and the transition in the line 42 marking the end of the long space or control signal starts the timing of the first bit receiving interval. The timing circuit 49 controls a gate in conjunction with the signals representing transitions in the condition of the signaling line 42 to supply signals representing binary 1s or Os to an input stage of the shift register 50 which is shifted or advanced incident to each transition. In this manner, the shift register 50 is loaded with a permutation or combination of binary 0s and 1s in accordance with the transition address from the central ofiice 40.

At the conclusion of the address transmitting operation, the setting of each of the shift registers is compared with the known address in each of the home units 44 and 46, and the single home unit in which the received address is the same as the home units designation is prepared to transmit a reply to the central office 40. Assum 5 ing that the home unit 46 has been selected by the central office 40, a data transmitting circuit is placed in an operative condition by the satisfactory completion of the checking operation, and a binary 1 is supplied to the first stage of the shift register 50. This 1 is then shifted to the next stage in which it provides an enabling signal to the first encoding gate in the network. The presence of a binary 1 or a binary representing the onoff condition of the first television receiver controls the transmitting network to transmit a long or short signal representing this information over the signaling line 42 to the central office 40. The transition in the signaling line 42 produced by the transmission of this data item shifts the 1 stored in the shift register to the next adjacent stage and interrogates the next encoding gate of the network 48. This operation continues step-by-step until all of the information stored in the home unit 46 has been transferred over the signaling line 42 to the central ofiice 40. At this time, the home unit 46 is restored to its receive condition.

The timing units, such as the timing circuit 49 in the home unit 46, are continuously operative and are driven from a conventional 60 cycle alternating current potential source. The counting circuit 49 includes four flipflops 52, 54, 56, and 58 driven by a Schmitt trigger circuit 60. The 60 cycle potential source is coupled to the input of the trigger circuit 60 by an input transformer 62 and a pair of diodes 64 and 65 connected to the opposite terminals of a secondary winding 62a of the power transformer. Thus, the trigger circuit 66 is, in effect, driven by a frequency doubler and receives 120 positive-going pulses per second and provides corresponding output signals to the input of the counter stage provided by the flip-flop 52 to set and reset this counter stage at eight and one-third millisecond intervals. The output of the counter stage 52 is supplied to the input of the counter stage 54 so that this stage is set and reset at sixteen and two-thirds millisecond intervals. The output of the stage 54 is coupled to the input of the stage 56 so that this stage is set and reset at thirty-three and one-third millisecond intervals. The output of the counter stage 56 is coupled to only one input of the fourth stage 58 in the timing counter or circuit 49 so that this circuit is set at the end of a sixty-six and two-thirds millisecond interval. Thus, the counter stages 52, 54, and 56 are continuously set and reset, and the counter stage 58 is set under the control of the trigger circuit 60.

When the data handling system is in its normal condition, the central office 40 maintains the continuity of the signaling channel 42 or places this signaling loop in a closed circuit or mark condition so that the Winding of a receiving relay 66 is normally energized over a circuit including a fullwave rectifier bridge 68 and a pair of normally closed contacts 70a on a transmitting relay 70. The bridge 63 and the relay 70 are both a part of the home unit 46, and comparable components are provided in each of the other home units, such as the home unit 44. The energization of the receiving relay 66 normally maintains a pair of contacts 660 in an open condition.

When the central oihce 4i desires to interrogate one of the home units 44 or 46, the signaling loop 42 is placed in an open circuit or space condition for a period of more than one hundred milliseconds (133 and /3 milliseconds) to prepare the home units for receiving the subsequently transmitted address. When the signaling line 42 is placed in a space or open circuit condition, the energizing circuit for the receiving relay 66 is interrupted so that the contacts 66a are closed. The closure of these contacts places an inverter 72 in a nonconductive state to initiate the charging of a capacitor 7 4 with a negative potential supplied from the inverter 72 and drives a positive-going pulse from a capacitor 76 through an OR gate 78. This positive-going pulse is applied to the reset leads of the counter stages 52, 54, 56, and 5 8 and restores the counter 49 to a zero or normal condition. This posifive-going pulse is also applied to the reset input of a first stage in the shift register 50 and. to the shift inputs of the remaining stages 81-91. Approximately 58 milliseconds after the receipt of the positive pulse indicating the transition from the mark to space condition of the signaling line 42, the three counter stages 52, 54, and 56 are set to complete the enabling of a 1 AND gate 92. When the gate 92 is enabled, an inverter 94 is placed in conduction to supply a positive-going pulse to the set input of the input stage 80 of the shift register 50. Thus, a binary l is stored in the first stage 80. This bit provides one bit of a control code subsequent-1y shifted through the next nine stages of the shift register 50 to indicate the receipt of only the correct number of bits in the address transmitted from the central ofiice 40. The other bit of the control code is the 0 previously shifted to the stage 81 by the initial shift pulse.

At the end of approximately one hundred milliseconds, all of the inputs to a long space detecting AND gate 96 are enabled to provide a signal indicating that the signal received from the signaling line 42 is a long space or start control signal having a duration in excess of one hundred milliseconds. Two of the inputs to the gate 96 are enabled by the negative potentials supplied by the counter stages 56 and 53. The remaining input to the gate is enabled at the output of the inverter 72 which is maintained in a nonoonductive state because of the closed contacts 660 representing a space condition on the signaling line 42. When the AND gate 96 is enabled, an inverter 98 supplies a positive-going pulse through a capacitor 106* and an OR gate 102 to the reset input of a reply flip-flop 10-4 to insure that this flip-flop is in the reset condition. The inverter 98 also supplies a positive-going signal to the reset terminal of a line flip-flop 106 which controls the operation of the transmitting relay 70 to insure that this relay is released and that the contacts 70a are closed. The inlverter 98 also supplies a positive-going pulse through an OR gate 108 to a resetting conductor common to all of the stages 81-91 in the shift register 50, thereby resetting all but the input stage 80 of the shift register 50. The input stage 80 now stores the 1 bit previously supplied under the control of the AND gate 92.

At the end of the long space signal, the central ofiice 40 restores the signaling line 42 to a mark condition to initiate the transmission of the address individual to the desired one of the home units 44 or 46. Assuming that the home unit 46 is identified by the address 00110011, the central ofiice 40 first transmits a long signal representing 1 by maintaining the signaling line 42 in a closed circuit or mark condition for a period of around 75 milliseconds. When the line 42 is first returned to this mark condition, the energizing circuit for the receiving relay 66 is completed, and the contacts 662 are opened. This places the inverter 72 in a conductive condition so that the capacitor 74 supplies a positive-going pulse through the OR gate 78 is also applied to the reset iputs of the 81-91 and to the reset input of the input stage 80. Since the input stage 80 previously was set to a 1 condition, the first stage 81 is set to store the 1, and the remaining stages 82-91 remain in 0 conditions. The input stage 80 is reset to a 0 condition. The positive-going pulse provided by the OR gate 78 is also aplied to the reset inputs of the counter stages 52, 54, 56, and 58 in the timing circuit 49 so that these circuits are restored to a normal condition to start a new timing operation during which the duration of the mark condition of the signaling channel 42 wil be determined as an indication of whether the first bit of the transmitted address is a 1 or a 0.

Since the first bit of the transmitted address is 1 the mark condition persists for approximately seventy-five milliseconds. At the end of a fifty-eight millisecond period, the counter stages 52, 54, and 56 are set, and the gate 92 is again fully enabled so that the inverter 94 supplies a positive-going pulse to the set input of the input stage 80 of the shift counter 50. Thus, a 1 is now stored in the 7 input stage 80 representing the first bit of the transmitted address. At the end of the seventy-five millisecond interval, the central ofiice 40 returns the line 42 to a space condition to close the contacts 66a. This terminates the first transmitted bit of the address and initiates the second bit of the address which is also a long duration signal of seventy-five milliseconds representing a 1. When the contacts 66a are closed, the capacitor 76 and the OR gate 78 once again supply a positive-going pulse to the shift inputs of the stages 81-91 and shift ls into the counter stages. The positive-going pulse supplied by the gate 78 also resets the input flip-flop 80 and resets the stages 52, 54, 56 and 58 of the timing counter 49.

Since the duration of the second transmitted bit of the address is also a 1, the gate 92 is again enabled to control the inverter 94 to supply a positive-going pulse to the set input of the input stage 80 so that a 1 is again stored in the stage. Thus, at the end of the interval at which the second bit is transmitted, the return of the line 42 to a mark condition opens the contacts 660 to place the inverter 72 in a conductive condition so that the capacitor 74 forwards a positive-going pulse through the OR gate 78 to the shift inputs of the stages 81-91 and the reset input of the input stage 80. This sets the stages 81, 82, and 83 to store three 1s and resets the input stage 80, the stages 85-91 remaining in a representing condition. The pulse provided by the OR gate 78 also resets the counter 49 to its normal condition.

Since the third bit of the address of the unit 46 is a 0, the central ofiice 40 maintains the signaling line 42 in a mark condition for a period of around thirty-three milliseconds and then restores the line to a space condition so that the contacts 66a are again closed. At this time,

the capacitor 76 and the OR gate 78 provide a positivegoing pulse to the shift input leads of the counter stages 81-91 and resets the counter 49 and the input stage 80 of the shift register 50. Since the timing counter 49 does not reach a setting in Which all of the inputs to the 1 gate 92 are enabled, the input stage 80 is not set to store a 1, and the shift pulse now supplied by the OR gate 78 shifts a 0 into the first stage 81 and shifts the 1s into the counter stages 82, 83, and 84, the remaining stages in the shift register 50 being in a 0 representing condition. In this manner, the appearance of a shift signal at the output of the OR gate 78 at a time that is either prior to or subsequent to the enabling of the 1 gate 92 by the timing counter 49 controls the storage of ls or Us in the input stage 80. The appearance of the positive-going shift pulse at the output of the OR gate 78 is directly controlled by the transitions in the signaling line 42 between mark and space conditions, and these transitions are, in turn, determined by the lengths or durations of the signals transmitted by the central office 40.

The central office 40 continues to transmit the remaining five bits of the address comprising 00110 which are stored in the shift register 50 in the manner described above so that when the signaling line 42 goes from a space condition to a mark condition to supply the last shift pulse, the initial 0 is stored in the stage 90, the initial 1 is stored in the stage 89, the input stage 80 is reset, and the stages 81-88 are selectively set and reset to store the address 00110011, respectively. The home unit 46 remains in this condition until the mark signal applied to the signaling line 42 has persisted for approximately fifty-eight milliseconds. At this time, the 1 gate 92 is again enabled to drive the inverter 94 so that the input stage 80 of the shift register 50 is operated to a set condition. After one hundred milliseconds, the stages 56 and 58 of the timing counter 49 are set, and this setting of the counter initiates an operation in which the received address is compared or checked with the known address of each of the home units 44 and 46 to determine the home unit selected by the central office for transmission of a reply. This setting of the counter 49 does not enable the long space gate 96 because the right- 8 hand input to this gate receives an inhibiting potential from the conductive inverter 72.

The received address is checked in each of the home units 44 and 46 by an address gate similar to an address negative AND gate 110 (FIG. 1) in the home unit 46. The upper input to this gate is enabled because the line is in a mark condition, and the contacts 66a are opened so a negative potential is applied to the upper input. The next two inputs are connected to the set output of the stage and the reset out-put of the stage 89 in which is stored the preliminary code 1 which has been shifted through the register 50. The reset condition of the stage 98 and the set condition of the stage 89 insures that only the correct number of bits has been received from the central office 40. If an excess number of bits had been received, the 1 now stored in the stage 89 would have been shifted to the stage 90 to remove the enabling input from the second from the top input of the address gate 110. The stage 90 cannot be reset following a setting resulting from the receipt of an excessive number of address bits because a positive AND gate 112 which is connected to one input of the stage 90 is inhibited by the reply flip-flop 104 and prevents the shift pulses from resetting this stage. Further, if an inadequate number of bits had been received, the stage 89 in which the preliminary 1 is stored would not be in a set condition, and the third from the top input to the address gate would not be enabled. Thus, the stages 89 and 90 insure the presence of a correct number of bits in the address received from the signaling line 42, while the upper input to the gate 110 insures that the signaling line 42 is in the correct marking condition provided at the termination of the transmission of the address.

The next eight leads of the address gate110 are selectively interconnected with the set and reset outputs of the counter stages 81-88 in Which are stored the eight received bits of the address. Since the address individual to the home unit 46 is 00110011 and since the address gate 110 is a NAND gate, the reset outputs of the stages 88, 87, 84, and 83 are connected to the input of the gate 110 representing ls, and the set outputs of the stages 86, 85, 82, and 81 are connected to the input of the gate 110 representing 0s. The bottom two inputs to the address gate 110 are connected to the reset outputs of the counter stages 56 and 58 so that this gate is fully enabled only after the mark condition has persisted on the signaling line 42 for a period of approximately one hundred milliseconds.

When the address gate 110 is fully enabled, an output inverter 114 is placed in conduction to supply a positivegoing pulse to the set input of the reply flip-flop 104. The setting of the reply flip-flop 104 removes an inhibiting potential from an AND gate 116 connected to the complementing input of the line flip-flop 106. The setting of the reply flip-flop 104 also removes a clamping potential from six diodes 118, 120, 122, 124, 126, and 128 (FIG. 2) to enable the operation of the coding network under the control of the shift register 50. The setting of the reply flip-flop 104 also controls a capacitor 130 (FIG. 1) to supply a positive-going pulse to the reset input of a flip-flop 132 through an OR gate 134. The setting of the reply flip-flop 104 also partially enables the AND gate 112 and inhibits the 1 AND gate 92 so that the counter 49 no longer controls the selective setting of the input stage 80, this stage now being set to store a 1.

The positive-going pulse provided at the output of the inverter 114 in response to the enabling of the address gate 110 is also forwarded through the OR gate 108 to be applied to the reset inputs of the stages 81-91 of the counter. When these stages are all reset, the enabling potentials are removed from the address gate 110 to terminate the positive-going pulse provided by the inverter 114. Because of the speed at which the stages 81-91 are r reset, the inverter 114 provides a positive-going output pulse of a relatively short duration on the order of several microseconds.

The home unit 46 is now prepared to initiate the transmission of the repiy to the central ofiice. As indicated above, the selected home unit 46 transmits information to the central office 40 over the signaling channel 42 representing the on-off condition and the tuning condition of one or more Wave signal receivers located in the collaborators home under the control of the data storing or collecting means represented by the plurality of blocks indicated generally as 136 in FIG. 2. These means can comprise any suitable unit for supplying signals representing the operating conditions of the receivers and their tuning conditions. These units can comprise one or more switch controlled resistance matrix coding units of the type shown and described in detail in United States Patent No. 2,881,417. As an example, the units 136 can supply a low value alternating current potential to the encoding network 48 when the connected wave signal receiver is in an off condition and a higher value of alternating current potential when the connected receiver is in an on condition. Further, these units can apply a combination of high and low level alternating current potentials representing the binary values 1, 2, 4, and 8 in accordance with a coded representation of the selected channel. A high value alternating current potential represents a binary 1 and a lower value alternating current potential represents a binary 0.

These potentials are applied to the inputs of the encoding network 48 which is identical to the similar network shown and described in detail in the above-identified Currey et al. application. Two of the detecting and gating circuits included in the network 48 are illustrated in FIG. 2 and include storage capacitors 138 and 14d] selectively charged to high or low level negative potentials in accordance with the information to be transmitted. The capacitor 138 is charged to a high negative potential if the connected receiver is in an on condition and a low negative potential if the receiver is off. The capacitor 140 is charged to a high negative potential to represent a 1 and to a low negative potential to represent a 0. Similar means are provided in the encoding network 48 controlled by the remaining outputs from the translating matrix.

The diodes 118, 121i, 122, 124, 126, and 128 connected to the outputs of the flip-flop 164 prevent the loss of the charge on the capacitors 138 and 140 due to the operation of the shift register 50 during the address receiving operation. The capacitors in the gates controlled by the stages 87-91 have an adequate time in which to recover their proper charge levels before they are sampled during the transmitting operation and do not require diode controls. The setting of the flip-flop 104 biases the diodes 118, 120, 122, 124, 126, and 128 in a reverse direction to permit operation of the connected gates in accordance with the charges provided by the units 136.

The actual transmission of the reply from the home unit 46 to the central oflice 40 over the signaling channel 42 is initiated when the reply flip-flop 104 is set. At this time, all of the inputs to the AND gate 116 are enabled, and an inverter 141 applies a positive-going pulse to the complementing input of the line flip flop 106. This sets the flip-flop 1116 so that the winding of the transmitting relay 70 is energized. When the relay 78 is operated, the contacts 70a are opened to interrupt the continuity of the signaling loop 42. This, in turn, causes the release of the relay 66 so that the contacts 66a are closed. The closure of the contacts 66a again controls the OR gate 78 in the manner described above to supply a positive-going pulse to the shift inputs of the counter stages 81-91 and the reset input of the input stage 80. This shift pulse transfers the preliminary 1 stored in the input stage 80 to set the shift register stage 81. The positive-going ulse at the output of the R gate 78 also resets the timing counter 4? to its normal condition. In doing so, one of the enabling inputs for the gate 116 is removed, and the in- 18) verter 141 returns to a nonconductive state. However, this does not change the setting of the line flip-flop 106.

When the stage 81 is set in response to the shift signal resulting from the operation of the transmit relay 70, this stage forwards a positive-going pulse through a diode 142 in the coding network 48 individual to this stage to control the duration of the first bit of information transmitted over the line 42 to the central office 40. If the first wave signal receiver in the collaborators home is in an on condition, the capacitor 138 is charged to a more negative potential, and the positive-going pulse applied by the stage 81 places the diode 142 in conduction. Alternatively, if the first Wave signal receiver is in an off condition, the capacitor 138 is charged to a low negative potential, and the positive pulse does not place the diode 142 in conduction. This pulse is differentiated and supplies a positivegoing pulse through a diode 144 to a terminal 146. This terminal is connected to the lOWer input of an OR gate 148. This positive-going pulse is transmitted through the OR gate 148 to set the flip-flop 132. The setting of the fiip flop 132 provides an inhibit to one input of the gate 116.

The gate 116 thus remains disabled until such time as the counter stage 58 is set sixty-six milliseconds following the time at which the transmit relay 70 was operated to open the contacts 78a and place the signaling line 42 in its initial space condition. When the counter stage 58 is set, a capacitor 150 provides a positive-going signal through the OR gate 134 to reset the flip-flop 132. Since the counter stage 54 is now in a reset condition, the gate 116 is fully enabled and places the inverter 141 in a conductive condition so that the line flip-flop 186 is operated to its alternate or, in this instance, reset condition. In the reset condition of the line flip-flop 106, the winding of the transmit relay 70 is no longer energized, and the contacts 71111 are closed to return the line 42 to a marking condition. Thus, the home unit 46 transmits a long duration space signal on the order of sixty-six milliseconds to indicate that the first wave signal receiver in the collaborators home is in an off condition.

Referring back to the operation of the first gate in the encoding network 48 and assuming that the first wave signal receiver is in an on condition so that the capacitor 138 is charged to a high negative potential, the positivegoing signal provided by shifting a 1 into the stage 81 does not produce a positivegoing pulse in the difierentiating network. Thus, the flip-flop 132 is not set to inhibit the NAND gate 116. This me us that the gate 116 remains enabled and that the inverter 141 remains conductive to apply ground to the coupling capacitors in the complementing input to the flip-flop 106. When the counter 49 advances to a setting at which the stage 54 is set at the end of a sixteen millisecond interval, one input to the gate 116 is inhibited, the inverter 141 returns to a nonconductive state, and the coupling capacitors in the flipflop 106 begin to charge. Following another interval of around sixteen milliseconds, or thirty-three and one-third milliseconds after the initial transition to a space condition on the signaling line 42, the stage 54 returns to a reset condition, the gate 116 is enabled, and the inverter 141 is placed in conduction to apply positive-going operating pulses to the flip-flop 106. The flip-fiop now is reset to terminate the flow of current through the winding of the transmitting relay 70, and this relay returns to a normal condition to close the contacts 700. Thus, the home unit 46 maintains the signaling line 42 in a spacing condition for a short period of time representing a 0 to indicate that the first wave signal receiver is on and maintains the signaling line in a space condition for a longer duration representing a 1 to signify that the television receiver is in an 011 condition. The selective control over the duration of operation of the transmit relay 70 is determined by the selective setting of the control flip-flop 132.

When the signaling line 42 is returned to a mark condition at the termination of the transmission of the first bit representing the onoif condition of the first wave signal receiver, the receiving relay 66 is again operated to open the contacts 66a to provide a shift signal at the output of the OR gate 78 in the manner described above. This resets the timing counter 49 to a normal condition and shifts the 1 from the counter stage 81 to the counter stage 82. When the counter stage 82 is set, the second encoding gate in the network 48 is interrogated to determine whether a or a 1 is to be transmitted.

More specifically, when the counter stage 82 is set, a negative-going signal is applied to a diode 152. If the storage capacitor 140 is charged to a lower negative voltage representing a binary O, the diode 152 is placed in conduction, and no output signal is provided by the gate circuit. Alternatively, if the capacitor 140 is charged to a high negative potential representing a l, the diode 152 is not placed in conduction by the negative-going pulse, and this pulse is differentiated to provide a negative pulse that is forwarded through a diode 154 to a terminal 156 which is connected to the input of an inverter 158. This negative-going pulse places the inverter 158 in conduction so that the OR gate 148 provides a positive-going pulse for setting the control flip-flop 132. As set forth above, the setting of the control flip-flop 132 inhibits one input to the gate 116 so that the line flip-flop 106 cannot be operated to its alternate setting to reenergize the relay 70 until sixty-six milliseconds have elapsed and the stage 58 of the counter 49 is set. Thus, a longer duration mark signal is provided representing a 1. Alternatively, if the gate associated with the counter stage 82 does not provide a negative-going pulse at the terminal 156, the flipfiop 132 is not set, and the counter stage 54 controls the inverter 141 and the NAND gate 116 to set the line flipflop 106 at the end of thirty-three milliseconds to provide a short duration mark signal representing a 0.

At the end of either the long duration 1 period established by the set flip-flop 132 or the short duration 0 period determined by the counter stage 54, the line flipflop 106 is operated to its set condition to energize the winding of the relay 70 so that the contacts 70a are opened to return the signaling channel 42 to a space condition and to terminate the transmission of the second bit of the reply. At this time, the relay 66 is released to close the contacts 66a, and a shift signal is provided by the OR gate 78 to reset the timing counter 49 and to shift the single 1 from the stage 82 to the stage 83 of the shift register 50. The setting of the stage 83 in the shift register 50 interrogates the next encoding gate in the network 48 to transmit a l or 0 in the next order of the binary number.

The binary 1 is then shifted through the remaining stages 8491 to transmit the remainder of the reply to the signaling line 42 by selectively operating and releasing the transmitting relay '70 for varying periods of time in accordance with the 0 or 1 information to be transmitted to the central office 40. In this connection, the enabling of the gate 112 by the set flip-flop 104 permits the stages 90 and 91 to be set and reset in the usual fashion as part of the shift register.

Incident to the termination of the transmission of the eleventh or last bit of the reply, shown in the drawings as being a spare bit, the return of the relay '70 to a mark condition causes the resetting of all of the stages of the counter 50. Because the single 1 bit was stored in the last stage 91, when it was reset, a capacitor 160 supplies a positive-going signal through the OR gate 102 to reset the reply flip-flop 104. The resetting of the reply flip-flop 104 applies an inhibit to the gate 116, renders the clamping diodes 118, 120, 122, 124, 126, and 128 effective, inhibits the gate 112, resets the flip-flop 132, and partially enables the 1 gate 92. Thus, the home unit 46 has been restored to a condition in which it is prepared to receive subsequently transmitted addresses.

The home unit 46 also includes means controlled by the timing circuit 49 for insuring that the transmit relay 70 is not inadvertently left in an energized state interrupting the signaling line 42. More specifically, whenever the counting circuit 49 is advanced to a setting in which the counting stages 56 and 58 are set, representing an elapsed timed of one hundred milliseconds, and the line 42 isin a space condition so that the inverter 72 is in a nonconductive condition, the gate 96 is fully enabled. The gate 96 pulses the inverter 98 to supply a positive-going pulse to the reset input of the line flip-flop 106. This resets this flip-flop and terminates any inadvertent operation of the relay 70 to insure that the contacts 7011 are closed whenever the line 42 remains in a spacing condition for more than one hundred milliseconds. If the long space condition occurs during the transmission of a reply by the home unit 46, the timing circuit 49 controls the line flip-flop 106 in the manner described above to return the line to a mark condition and to interrupt the reply to indicate that incorrect information has been transmitted.

Although the present invention has been described with reference to a single illustrative embodiment thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention.

What is claimed and desired to be secured by Letters Patent of the United States is:

1. In a data handling system, a signaling channel providing different duration signals representing different data values, a shift register having a plurality of serially coupled stages including an input stage, means operative between successive signals on the channel for shifting stored data along the stages, timing means responsive to the different durations of the signals for storing different data values in the input stage, and means for resetting the timing means incident to each shifting operation.

2. In a data handling system, a signaling channel supplying ditferent duration signals, a shift register including an input stage, timing means operable through different d'uration timing cycles corresponding to the different duration signals, control means controlled by the timing means for setting the input stage of the shift register, and means responsive to signals received from the signaling channel for resetting the timing means and shifting the data stored in the shift register.

3. In a data handling system, a signaling channel providing signals of two different durations representing different data values, a shift register having an input stage and a plurality of other serially coupled stages, means controlled by the received signals and responsive to the end of each signal for shifting the values stored in the shift register, timing means operable through timing cycles of variable durations and reset to a beginning condition at the end of each signal, and means controlled by the timing means for setting the input stage to store different values in accordance with the different durations of the received signals.

4. In a data handling system, a signaling channel providing signals of two different durations representing different data values, a shift register having an input stage and a plurality of other serially coupled stages, a signal source for setting one value in the input stage and for shifting the values stored in the register, means controlled by the signaling channel for operating the signal source for each received signal of either duration, control means for setting a different value in the input stage, and timing means responsive to the duration of the signals received from the signaling channel for operating the control means when the received signal has a given one of the two different durations.

5. In a data handling system, a signaling channel providing different duration signals representing different data values, a shift register having a plurality of serially coupled stages including an input stage, control means responsive to the signals received from the signaling channel for shifting the data stored in the shift register incident to each signal received from the channel, means included in the control means for storing a data entry of one given value in the input stage for each signal received regardless of the duration of the signal, timing means, and means controlled by the timing means for changing the value of the data entry stored in the input stage when the duration of the received signals has a predetermined duration.

6. In a data handling system, a signaling channel supplying different duration signals, a shift register including an input stage, timing means operable through different duration timing cycles corresponding to the different duration signals, control means controlled by the timing means for setting the input stage of the shift register, means responsive to signals received from the signaling channel for resetting the timing means and shifting data stored in the shift register, gate means connected to the shift register, and means controlled by the gate means when a predetermined data item is stored in the shift register for disabling the control means.

7. In a data handling system, a source of sequential signals representing a message having a given number of hits, a shift register having a number of stages greater than the given number, means for entering a known check code in the shift register, means controlled by the source for sequentially entering the bits of the message in the shift register so that the check code and the bits of the message are shifted along the register, detecting means for checking the check code, and means controlled by the detecting means for providing an indication that the given number of bits have been received.

8. In a data handling system for receiving a message having signals representing a given number of message bits, a shift register having a plurality of serially coupled stages, control means for storing a check code in the shift register, input means controlled by the signals for storing the message bits in the register and for shifting the check code and the message bits along the register, message utilizing means controlled by the shift register, and checking means controlled by given ones of the stages in the shift register and responsive to the arrival of the check code at the given stages for at least partially enabling the message utilizing means.

9. In a data handling system, a signaling line, a transmitting switch operable to open and close said line, bistable means for controlling the operation of said switch, data input means for controlling the operation of the bistable means to transmit data supplied by the data input means, timing means, and means controlled by the timing means and responsive to the open and closed conditions of the signaling line for controlling the switch to place the line in a closed circuit condition whenever the line remains in an open condition for a predetermined period of time.

10. In a data handling system, a signaling line, a transmitting switch operable to open and close said line, bistable means for controlling the operation of said switch, data input means for controlling the operation of the bistable means to transmit data supplied by the data input means, a continuously operable timing means, means for resetting 14: the timing means to a normal condition in response to placing the line in a closed circuit condition, and means controlled by the timing means and responsive to an open condition of the line for operating the switch to close the line whenever the line remains in an open condition for a given length of time.

11. In a data handling system, a signaling channel, transmitting means for alternately interrupting and establishing the continuity of the channel, a bistable circuit for controlling the operation of the transmitting means, said bistable circuit maintaining the transmitting means in a normal condition establishing the continuity of the channel, data storing means, means controlled by the data storing means for operating the bistable circuit to control the transmitting means to transmit the stored data, continuously operative timing means, and means controlled by the timing means and the condition of the channel for controlling the bistable circuit to operate the transmitting means to a condition establishing channel continuity whenever the channel is interrupted for more than a predetermined period of time.

12. In a data handling system, a signaling channel from which different duration signals are received and over which different duration signals are transmitted, said different duration signals representing different data values, a shift register, means controlled by signals received from the channel for storing the data values represented thereby in the shift register, detecting means for checking the data stored in the register to determine whether the stored data corresponds to predetermined data, transmitting means for transmitting different duration signals over the channel, data input means for supplying a plural bit data item to be transmitted, and means controlled by the detecting means for shifting a single data value through the shift register to render the different data bits in the item to be transmitted effective to control the transmitting means.

13. In a data handling system, a signaling channel from which plural bit message signals are received and over which plural bit message signals are transmitted, a plural state shift register having an input stage, means controlled by signals received from the channel for storing the received message in the shift register by storing successively received bits in the input stage and shifting the received bits to subsequent stages as additional bits are received, detecting means controlled by the shift: register for determining whether the message stored in the shift register corresponds with a known message, storing means for storing a plural bit reply message, transmitting means for transmitting the plural bit reply message over the channel, a plurality of gate means controlled by the storing means and the shift register, and means controlled by the detecting means and operative to store a data bit in the input stage of the shift register and to shift the data bit through the shift register to enable the gate means to control the transmitting means to transmit the reply message.

No references cited.

ROBERT C. BAILEY, Primary Examiner. R. ZACHE, Assistant Examiner. 

1. IN A DATA HANDLING SYSTEM, A SIGNALING CHANNEL PROVIDING DIFFERENT DURATION SIGNALS REPRESENTING DIFFERENT DATA VALUES, A SHIFT REGISTER HAVING A PLURALITY OF SERIALLY COUPLED STAGES INCLUDING AN INPUT STAGE, MEANS OPERATIVE BETWEEN SUCCESSIVE SIGNALS ON THE CHANNEL FOR SHIFTING STORED DATA ALONG THE STAGES, TIMING MEANS RESPONSIVE TO THE DIFFERENT DURATIONS OF THE SIGNALS FOR STORING DIFFERENT DATA VALUES IN THE INPUT STAGE, AND MEANS FOR RESETTING THE TIMING MEANS INCIDENT TO EACH SHIFTING OPERATION. 